The present invention relates to managing memory page tables in a processing system, and more specifically, to joining page table entries in a processing system.
Processors including central processing units (CPUs) may use translation lookaside buffers (TLB) as caches that improve virtual address translation speed. The TLBs are used to map virtual and physical addresses spaces and includes page table entries that map the virtual addresses to the physical addresses.
Several address translation mechanisms are used in computer systems. In PowerPC® by IBM, for example, an effective address is translated to a corresponding real address by way of page table entries found by selecting an ESID table entries associated with the effective address, and using the entry to locate a group of page table entry by way of a hashing algorithm. In zArchitecture®, also by IBM, for another example, an effective address is translated to a corresponding real address by way of a hierarchy of translation tables, translation tables are indexed by a portion of the effective address to find the address of the next translation table of the hierarchy until a real (or absolute) address is obtained. Thus, the PowerPC address translation maps a 64 bit effective address (of a large range of memory (264 bytes)) in only 2 levels (an SLB table entry and page table entry), while zArchitecture hierarchical address translation requires 5 tables to translate a large effective address range (264 bytes). Both address translation mechanisms provide advantages to respective operating systems.
EP690386A1 Jan. 3, 1996 “Address translator and method of operation”, incorporated herein by reference teaches a CAM/SRAM structure (44) performs address translations that are compatible with a segmentation/paging addressing scheme yet require only a single look-up step. Each entry in the effective-to-real-address-translator has two CAM fields (ESID, EPI) that independently compare an input segment identifier and an input page identifier to a stored segment identifier and a stored page identifier, respectively. The ERAT outputs a stored real address field (DATA) associated with a stored segment-stored page pair if both comparisons are equivalent. The ERAT can invalidate stored translations on the basis of segment or page granularity by requiring either a segment or a page CAM field match, respectively, during an invalidate operation.
U.S. Pat. No. 8,103,851B2 Jan. 24, 2012 “Dynamic address translation with translation table entry format control for identifying format of the translation table entry” incorporated herein by reference teaches an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1 M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.